Magnetic-core memory

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Magnetic-core memory is the dominant form of random access computer memory for 20 years between about 1955 and 1975. Such memory is often simply called core memory , or, informally, core .

Core uses small magnetic toroids (rings), the core , where the cable is threaded to write and read information. Each core represents a single bit of information. The nucleus can be magnetized in two different ways (clockwise or counterclockwise) and the bits stored in the nucleus are zero or one depending on the magnetic orientation of the core. Cables are arranged to allow individual cores to be adjusted to either one or zero and for magnetization to be changed by sending the right electrical current pulse through the selected cable. The process of reading the core causes the core to be reset to zero, thus removing it. This is called destructive reading . When not read or written, the core retains the last value they have, even when the power is off. This makes them not easy to change .

Using smaller cores and wires, the core memory density gradually increased, and by the late 1960s the density of about 32 kilobits per cubic foot was typical. However, achieving this density requires very careful preparation, almost always done by hand despite major repeated attempts to automate the process. The cost decreases during this period from about $ 1 per bit to about 1 cent per bit. The introduction of the first semiconductor memory SRAM chip in the late 1960s began to erode the core market. The first successful DRAM, Intel 1103 which arrived in number in 1972 at 1 cent per bit, marked the beginning of the end of the core. Improvements in semiconductor manufacturing led to a rapid increase in storage and price reductions that pushed the core of the market around 1974.

Although core memory is outdated, any computer memory is sometimes still called "core"; in particular, files that record the contents of memory after a system error is usually called a core dump.

Video Magnetic-core memory

History

Developer

The basic concept of using square hysteresis loops from certain magnetic materials as storage or switching devices has been known since the early development of computers. Much of this knowledge has evolved due to an understanding of transformers, which allows the reinforcement and performance of such a switch when constructed using certain materials. The stable switching behavior has been known in the field of electrical engineering, and its application in the computer system immediately. For example, J. Presper Eckert and Jeffrey Chuan Chu have done some development on the concept in 1945 at Moore School during ENIAC's efforts.

Frederick Viehe filed numerous patents on the use of transformers to build digital logic circuits in lieu of logic relays that began in 1947. The patents on a fully developed core system were granted in 1947, and subsequently purchased by IBM in 1956. These developments are little-known, however, and major core developments are usually associated with three independent teams.

Substantial work on the ground was done by the Shanghai-born American physicist, An Wang and Way-Dong Woo, who invented the pulse transfer controller in 1949. His name refers to the way the magnetic field. of the core can be used to control the current switching in the electromechanical system. Wang and Woo worked at the Harvard University Computing Laboratory at the time, and the university was not interested in promoting inventions made in their laboratories. Wang is able to patent his own system.

MIT's whirlwind computers require fast memory systems for real-time aircraft tracking. Initially, the Williams tube - a cathode-ray tube-based storage system - was used, but the device was always temperamental and unreliable. Some researchers in the late 1940s understood the idea of ​​using magnetic cores for computer memory, but Jay Forrester received a major patent for his discovery of accidental core memory that enabled the storage of 3D information. William Papian from Project Whirlwind called one of these efforts, Harvard's "Static Magnetic Static Delay", in an internal memo. The first core memory of 32 x 32 x 16 bits was attached to Whirlwind in the summer of 1953. Papian explains: "Magnetic-Core storage has two major advantages: (1) greater reliability with reduction due to maintenance time intended for storage; 2) shorter access time (core access time is 9 microseconds: tube access time approx 25 microseconds) thus increasing the speed of computer operation. "

In April 2011, Forrester recalled, "the use of Wang cores has no effect on the development of my random access memory.My Wang memory is expensive and complicated.As I recall, that may not be entirely correct, it uses two cores per binary bit and is essentially a delay line which moves a little forward.As far as I may have focused on it, that approach is not suitable for our purposes. "He described the discovery and related events, in 1975. Forrester has since observed," It took us about seven years to convince the industry that access- random core-magnetic memory is the solution to the missing link in computer technology.Later we spent after seven years in a patent court convincing them that they never thought about it first. "

The third developer involved in initial core development is Jan A. Rajchman at RCA. A productive inventor, Rajchman designed a unique core system using a ferrite band wrapped around a thin metal tube, building his first example using aspirin converted in 1949. Rajchman will also continue to develop a Williams tube version and lead the development of Selectron.

Two key discoveries led to the development of magnetic core memory in 1951. The first, An Wang, is a write-after-read cycle, which solves the problem of how to use storage media where read acts are erased reading data enabling serial development, one-dimensional shift register of o (50) bits, using two cores to store a bit. The core register list Wang was in the Revolution exhibition at the Computer History Museum. The second, Jay Forrester, is the current coincident system, which allows a small number of cables to control a large number of cores that allow 3D memory arrays of several million bits for example. 8K x 8K x64 bit.

The first use of the core is on the Whirlwind computer, and "the most notable contribution of the Whirlwind Project is random access, a magnetic core storage feature." Commercialization followed quickly. The magnetic core is used in the peripherals of the IBM 702 that was delivered in July 1955, and then in 702 itself. IBM 704 (1955) and Ferranti Mercury (1957) used core-magnetic memory.

It was during the 1950s that Seeburg developed the use of ferrite core memory storage which happened to be in the "Tormat" memory of its new jukebox, starting with the V200 released in 1955. The construction work was completed in 1953. Widely used in computing, telephone and industrial control followed.

Patent disputes

Wang's patent was not granted until 1955, and by that time the core was already in use. It started a series of lengthy lawsuits, which eventually ended when IBM purchased a patent directly from Wang for US $ 500,000 . Wang used the funds to broaden Wang Laboratories extensively, which he co-founded with Dr. Ge-Yao Chu, a schoolmate from China. In 1964, after years of struggling with the law, IBM paid MIT $ 13 million for Forrester patents - the largest patent settlement on that date.

The Forrester-powered accidental system requires one of the cables to run at 45 degrees to the core, which proves impossible to wire with the engine, so the core arrangement must be assembled under a microscope by workers with fine motor control. Initially, garment workers were used. In the late 1950s, industrial plants had been established in East Asia to build the core. Inside, hundreds of workers hung the core to pay low. This lowered core costs to the point where it became largely universal as main memory in the early 1960s, replacing both low-performance drum memory and expensive high-performance systems using vacuum tubes, and then transistors, as memory. The cost of core memory declined sharply over the lifetime of the technology: costs ranging from US $ 1.00 per bit and down to around US $ 0.01 per bit. Core was replaced by an integrated semiconductor RAM chip in the 1970s.

The core memory is part of a family of related technologies, now largely forgotten, that exploit the magnetic properties of the material to perform switching and amplification. In the 1950s, electronic vacuum tubes were well developed and highly sophisticated, but tubes had a limited lifetime, used more power, and were much larger than semiconductors or magnetic technology, and the characteristics of their operations changed over their lifetime. Magnetic devices have many virtues from discrete and integrated solid-state devices that will replace them, and are extensively used in military applications. An important example is the MOBIDIC portable computer (truck-based) developed by Sylvania for the United States Army Signal Corps in the late 1950s. The contents of the electronic memory are lost when power is lost, but the core memory does not fluctuate and store its contents.

Maps Magnetic-core memory

Description

The term "nucleus" is derived from a conventional transformer whose rolls surround the magnetic core. In core memory, cables go through once through a given core - they are single-turn devices. The properties of materials used for memory cores are dramatically different from those used in power transformers. Magnetic materials for core memory require high magnetic remanents, the ability to remain highly magnetized, and low coercitivity so less energy is required to change the direction of magnetization. The core can take two states, encode a bit, which can be read when "selected" by "sense wire". The content of core memory is maintained even when the memory system is turned off (non-volatile memory). However, when the core is read, it is reset to a "zero" value. The circuitry in the computer's memory system then returns the information in the rewriting cycle immediately.

How core memory works

The most common form of core memory, X/Y line coincident-current, is used for the computer's main memory, composed of a large number of small ferromagnetic feroidetic ferrites ( cores ) united in a grid structure (arranged as a "stack" layer called plane ), with wires woven through a hole in the center of the core. In the initial system there are four cables: X , Y , Sense , and Hampers , but then the cores merge the last two cable into one Sense/Inhibit line. Each toroid is stored one bit (0 or 1). One bit in each plane can be accessed in one cycle, so every word of the word machine is worded over the "pile" of the plane. Each plane will manipulate a single word bit in parallel, allowing the full word to be read or written in one cycle.

Core relies on the "square loop" properties of the ferrite material used to make toroids. The electric current in the wire passing through the core creates a magnetic field. Only magnetic fields greater than a certain intensity ("select") can cause the nucleus to change the magnetic polarity. To select a memory location, one of the X and one of the Y lines is pushed with the half-current ("half-select") required to cause this change. Only the combined combined magnetic field where X and Y lines cross (the logical AND function) is sufficient to change the state; the other cores will only see half the required fields ("half selected"), or none at all. By moving the current through the cable in a particular direction, the induced field generated forces the nuclear magnetic flux selected to circulate in one direction or another (clockwise or counterclockwise). One way is saved 1 , while others are saved 0 .

The toroidal shape of the nucleus is preferred because the magnetic path is closed, there is no magnetic pole and thus very little external flux. This allows the core to be packed together tightly without letting the magnetic field interact. The 45-degree position alternately in the core arrangement helps reduce any stray clutch.

Read and write

To read a small amount of core memory, the circuit tries to reverse the bit to the polarity set to state 0, by directing the selected X and Y lines intersecting at the core.

• If the bit is 0, the physical state of the core is not affected.
• If the previous bit is 1, then the core changes the magnetic polarity. This change, after a delay, induces a voltage pulse to the Sense line.

Such pulse detection means that the last bit contains 1. The absence of a pulse means that the bit has contained 0. The delay in feeling the voltage pulse is called access time of the core memory.

After reading like that, the bit contains 0. This illustrates why the core memory access is called destructive reading : Any operation that reads the content of the core deletes that content, and they must be reinvented immediately..

To write a small amount of core memory, the circuit assumes there is a read operation and the bit is in state 0.

• To write 1 bit, the selected X and Y lines are moved, with the current in the opposite direction as for the read operation. Like reading, the nucleus at the intersection of lines X and Y changes the magnetic polarity.
• To write 0 bits (in other words, to inhibit the writing of 1 bit), the same amount of current is sent through the Inhibit path. This reduces the net current flowing through each nucleus to half the select current, inhibiting the change in polarity.

Access time plus rewrite time is cycle time memory .

Sense wire is only used when reading, and the Hambat wire is only used during writing. For this reason, then the core system combines the two into one wire, and uses a circuit in the memory controller to replace the wire function.

The core memory controller is designed so that each reading is immediately followed by a post (since reading forces all bits to 0, and since the assumed text has occurred). Computers began to take advantage of this fact. For example, the value in memory can be read with post-increment almost as fast as it can be read; the hardware simply adds value between the read and write phases of a single memory cycle (presumably indicating the memory controller to pause in the middle of the cycle). This may be twice as fast as the process of getting values ​​with read-write cycles, incrementing values ​​in multiple processor registers, and then writing new values ​​with other read-write cycles.

Another form of core memory

Pathway core memory is often used to provide memory registers. Other names for this type are linear select and 2-D . This form of core memory typically weaves three cables through each core on the plane, word read , write words , and bit sense/write . To read or remove words, full flow is applied to one or more words read words ; this clears the selected cores and any flip that induces the voltage pulses in their bit sense/write lines. To read, usually only one word read the word selected; but for clear lines, many read words can be selected when the bit sense/write line is ignored. To write a word, half the current is applied to one or more words write the word , and half the current is applied to each bit sense/write path for a bit to be arranged. In some designs, word read and word write languages ​​are combined into one wire, producing a memory array with only two cables per bit. To write, several lines write the word can be selected. It offers performance advantages over X/Y line coincident-current in some words that can be deleted or written with the same value in one cycle. The typical machine register set usually uses only one small field of this core memory form. Some very large memory is built with this technology, for example the extra memory of Core Storage Extension (ECS) on CDC 6600, which is up to 2 million 60-bit words.

Another form of core memory called core string memory provided read-only storage. In this case, cores, which have more linear magnetic material, are used only as transformers; no information is actually stored magnetically inside the individual core. Each word bit has one core. Reading the contents of the given memory address produces a current pulse in the wire corresponding to that address. Each address wire is threaded either through the core to denote binary [1], or around the outside of the core, to denote binary [0]. As expected, cores are much larger physically than the read-write core memory. This type of memory is very reliable. An example is the Apollo Guidance Computer used for moon landing.

Physical Characteristics

Early core memory performance can be characterized in current terms as very roughly proportional to 1 MHz clock rate (equivalent to home computers of the early 1980s, such as the Apple II and Commodore 64). The initial core memory system had a cycle time of about 6 Ã,Âμs, which had dropped to 1.2 Ã,Âμs in the early 1970s, and in the mid-70s fell to 600 ns (0.6 Ã,Âμs). Some designs have much higher performance: CDC 6600 has a memory cycle time of 1.0 Ã,Âμs in 1964, using cores that require half-select current of 200 mA. Everything possible is done to reduce access time and increase data rate (bandwidth), including simultaneous use of several core grids, each storing one bit of said data. For example, a machine may use 32 core grids with one bit of 32-bit words in each, and the controller can access all 32-bit words in a single read/write cycle.

Core memory is non-volatile storage - it can store its content indefinitely without power. It is also relatively unaffected by EMP and radiation. This is an important advantage for some applications such as industrial first-generation programmable controllers, military installations and vehicles such as fighter aircraft, as well as spacecraft, and causes the core to be used for several years after the availability of MOS semiconductor memory (see also MOSFET). For example, the Space Shuttle computer initially used the core memory, which stored memory contents even through the Challenger splash and subsequently plunged into the sea in 1986. Other initial core characteristics were that coercive force is very sensitive to temperature; the correct half-select current at one temperature is not a precise half-select current at another temperature. So the memory controller will include a temperature sensor (usually a thermistor) to adjust the current level correctly for temperature changes. An example of this is the core memory used by Digital Equipment Corporation for their PDP-1 computers; this strategy continues through all advanced core memory systems built by DEC for PDP line of air-cooled computers. Another method to handle temperature sensitivity is to attach a "pile" magnetic core in a temperature controlled oven. An example of this is the memory of the hot-air core of the IBM 1620 (which can take up to 30 minutes to reach operating temperature, about 106 ° F (41 ° C) and fuel-core heating-fuel from IBM 7090, IBM 7094 start, and IBM 7030.

The heated core is not cooled because the main requirement is consistent temperature , and it's easier (and cheaper) to maintain a constant temperature well above room temperature than one at or below it.

In 1980, the price of 16 kW core board (kiloword, equivalent to 32 kB) was fitted to a DEC Q-bus computer about US $ 3,000 . At that time, the supporting core and electronic compositions fit on a single printed circuit board measuring approximately 25 × 20 cm, the core arrangement is mounted several mm above the PCB and protected by metal or plastic plates.

Diagnosing hardware problems in core memory requires a time-consuming diagnostic program to run. While a quick test is checked if each bit can contain one and zero, this diagnostic tests the core memory with the worst case pattern and should run for several hours. Since most computers only have a single core memory board, this diagnostic also moves itself in memory, making it possible to test every bit. An advanced test is called a "Schmoo test" in which a half-select current is modified along with the time at which the taste line is tested ("strobed"). The data plot of this test seems to resemble a cartoon character called "Schmoo," and the name is stuck. On many occasions, the error can be solved by tapping the printed circuit board with the core arrangement on the table. This slightly alters the core position along the cable through it, and can fix the problem. The procedure is rarely needed, because the core memory proved to be very reliable compared to other computer components that day.

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See also

• Delay line memory
• Core buildup
• Strap core memory
• Line memory
• Bubble Memory
• Thin film memory
• MRAM
• Ferroelectric RAM
• Electronic Calculators - Some early desktop models use magnetic core memory.

src: cf.ppt-online.org

References

Patent

• AS. Patent 2,667,542 "Electrical connectors" (matrix switch with iron core operating as a cross-point switch A series of analog signal input or telephone X can be forwarded to output Y.), filed in September 1951, issued January 1954
• AS. Patent 2,708,722 "Device control of transfer credit", An Wang filed October 1949, published in May 1955
• AS. Patent 2,736,880 "multicoordinate digital information storage device" (coincident-current system), Jay Forrester filed May 1951, issued February 28, 1956
• AS. Patent 2,970,291 "Electronic Relay Circuit" (Patent Note "My discovery relates to electrical circuits using relays...") filed May 28, 1947, issued Jan. 31, 1961.
• AS. Patent 2,992,414 "Memory Transformer" (Patent notes that "My discovery relates to electrical relay circuits and more specifically to enhance transformers for use in them.") Filed May 29, 1947, issued July 11, 1961.
• AS. Patent 3,161,861 "Magnetic core memory" (repair) Ken Olsen filed November 1959, issued in December 1964
• AS. Patent 3,264,713 "Methods for Making Memory Core Structures" ("Patent Recording" Note This invention relates to magnetic memory devices, and more particularly to new and improved memory core structures and similar methods of manufacture... ") filed January 30, 1962 , issued August 9, 1966.
• AS. Patent 3.421.152 "Linear select magnetic memory system and control for it", W. J. Mahoney, issued Jan. 7, 1969
• AS. Patent 4,161,037 "Memory of ferrite core" (automatic production), July 1979
• AS. Patent 4,464,752 "Some hardened core memory events" (radiation protection), August 1984

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External links

• Interactive Java Tutorial - Magnetic Core Memory National National Laboratory
• Core Memory at Columbia University
• Navy Manual
• Core Memory on PDP-11
• The core memory and other types of early memory accessed April 15, 2006
• Current Conditional Core Ferrite Event Byte Magazine , July 1976
• Casio AL-1000 calculator - Displays the close range of magnetic core memory in this desktop electronic calculator from the mid-1960s.
• Still using core memory on some devices in the German computer museum
• A 110-Nanosecond Ferrite Core Memory
• background on core memory for computer

Source of the article : Wikipedia